Texas Instruments TMS320C3x User Manual
Page 757
Index
Index-16
timer-period register, definition
timing
external interface
expansion bus I/O cycles
primary bus cycles
external memory interface
TMS320C30
architecture, block diagram
DMA controller
arbitration
external memory interface
interrupt vector table
memory maps
memory organization, block diagram
serial ports
timers
TMS320C31
architecture, block diagram
boot loader
DMA controller
arbitration
external memory interface
interrupt and trap memory maps
interrupt vector table
memory maps
memory organization, block diagram
serial ports
timers
TMS320C32
architecture, block diagram
boot loader
data memory
data types and sizes
DMA controller
arbitration
external memory interface
interrupt vector table
memory, external widths
memory organization, block diagram
program memory
serial ports
short floating-point format
timers
trap vector locations
TMS320C3x
device differences
devices
compared
DSPs, introduction
functional block diagram
TMS320C3x (continued)
key specifications
serial port interface examples
TMS320LC31, power management mode, LOPOW-
ER
transfer-counter register
trap
conditionally instruction (TRAPcond)
flow, block diagram
initialization
interrupt considerations, ’C30
operation
vector locations
traps
two parallel stores, instruction word format
U
unsigned-integer format
single-precision
V
variable data-rate timing operation
burst mode
continuous mode
W
wait state
definition
generation
programmable
wait-state generator, definition
X
XF0, XF1 signals
Z
zero condition flag
zero fill, definition
zero wait-state
zero-logic interconnect of devices
zero-overhead looping