Texas Instruments TMS320C3x - Manual (Page 619)

Multiply Integer, 3-Operand MPYI3
13-161 Assembly Language Instructions
Syntax MPYI3 src2, src1, dst
Operation src1
×
src2
→
dst
Operands src1 3-operand addressing modes (T):
0 0 any CPU register
0 1 indirect ( disp = 0, 1, IR0, IR1)
1 0 any CPU register
1 1 indirect ( disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
0 0 any CPU register
0 1 any CPU register
1 0 indirect ( disp = 0, 1, IR0, IR1)
1 1 indirect ( disp = 0, 1, IR0, IR1)
dst register (R n, 0
≤
n
≤
27)
Opcode
31 24 23 16 8 7 0 15
0 0 1 0 0 1 0 0 1 dst T src1 src2
Description The product of the src1 and src2 operands is loaded into the dst register. The
src1 and src2 operands are assumed to be 24-bit signed integers. The result
is assumed to be a signed 48-bit integer. The output to the
dst register is the
32 LSBs of the result.
Integer overflow occurs when any of the 16 MSBs of the 48-bit result differs
from the MSB of the 32-bit output value.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C Unaffected
OVM Operation is affected by OVM bit value. Mode Bit