Texas Instruments TMS320C3x - Manual (Page 39)

Overview
2-3 Architectural Overview
Figure 2–1. TMS320C30 Block Diagram
SHZ
ARAU0 ARAU1
DISP0, IR0, IR1
ЙЙ
ЙЙ
ЙЙ
ЙЙ
ALU
32-bit
barrel
shifter
PC
RAM
block 1
(1K
Ч
32)
ЙЙЙЙЙ
ЙЙЙЙЙ
ЙЙЙЙЙ
ЙЙЙ
ЙЙЙ
ROM
block
(4K
×
32)
Cache
(64
×
32)
RAM
block 0
(1K
×
32)
RDY
HOLD
HOLDA
STRB
R/W
D31–D0
A23–A0
RESET
IR
CPU1
REG1
REG2
Й
Й
Й
Й
Й
Й
Й Й
Й
Й
Й
XRDY
MSTRB
IOSTRB
ЙЙЙ
ЙЙЙ
XR/W
XD31–XD0
XA12–XA0
40
32
32
32
32
32
32
32
24
24
24
24
BK
Extended-
precision
registers
(R7–R0)
Auxiliary
registers
(AR0–AR7)
Other
registers
(12)
40
40
40
40
Multiplier
DMA controller
Global-control
register
Source-address
register
Destination-
address
register
Serial port 0
Port-control
register
R/X timer
register
Data-transmit
register
Data-receive
register
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
Serial port 1
ЙЙЙ
ЙЙЙ
R/Xtimer
register
ЙЙЙЙЙ
ЙЙЙЙЙ
ЙЙЙЙЙ
ЙЙЙЙЙ
ЙЙЙЙ
Data-transmit
register
Data-receive
register
FSX1
DX1
CLKX1
FSR1
DR1
CLKR1
Timer0
Global-control
register
Timer-period
register
Timer-counter
register
TCLK0
Timer1
Global-control
register
Timer-period
register
Timer-counter
register
TCLK1
Port control
Primary
Expansion
Transfer-
counter
register
PDATA bus
PADDR bus
DDATA bus
DADDR1 bus
DADDR2 bus
DMADATA bus
DMAADDR bus
24
40
32 32 24 24 32 24
INT3–0
IACK
MC/MP
XF(1,0)
VDD(3-0)
IODVDD(1,0)
ADVDD(1,0)
PDVDD
DDVDD(1,0)
MDVDD
VSS(3-0)
DVSS(3–0)
CVSS(1,0)
IVSS
VBBP
SUBS
X1
X2/CLKIN
H1
H3
EMU6-0
RSV10–0
32 24 24 24 24 32 32 32
CPU2
32 32 40 40
Multiplexer
Multiplexer
Controller
CPU1
REGISTER 1 REGISTER2
Peripheral Data Bus
Peripheral Address
Bus
Multiplexer
ЙЙЙЙ
ЙЙЙЙ
Port-control
register
Legend:
PDATA bus – program data bus
PADDR bus – program address bus
DDATA bus – data data bus
DADDR1 bus – data address 1 bus
DADDR2 bus – data address 2 bus