Texas Instruments TMS320C3x - Manual (Page 557)

Floating-Point-to-Integer Conversion FIX
13-99 Assembly Language Instructions
Syntax FIX src, dst
Operation fix (src)
→
dst
Operands src general addressing modes (G):
0 0 register (R n, 0
≤
n
≤
7)
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst any CPU register
Opcode
31 24 23 16 8 7 0 15
0 0 0 0 0 1 G dst src 0 1 0
Description The floating-point operand src is rounded down to the nearest integral value
less than or equal to floating-point value, and the result is loaded into the dst
register. The src operand is assumed to be a floating-point number and the dst
operand a signed integer.
The exponent field of the dst register (bits 39–32) is not modified.
Integer overflow occurs when the floating-point number is too large to be repre-
sented as a 32-bit 2s-complement integer. In the case of integer overflow, the
result is saturated in the direction of overflow.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C Unaffected
OVM Operation is not affected by OVM bit value. Mode Bit