Texas Instruments TMS320C3x - Manual (Page 49)

Memory Organization
2-13 Architectural Overview
2.5 Memory Organization
The total memory space of the ’C3x is 16M (million) 32-bit words. Program,
data, and I/O space are contained within this 16M-word address space, allowing
the storage of tables, coefficients, program code, or data in either RAM or
ROM. In this way, memory usage is maximized and memory space allocated
as desired.
2.5.1 RAM, ROM, and Cache
Figure 2–5 shows how the memory is organized on the ’C30. RAM blocks 0
and 1 are each 1K
32 bits. The ROM block, available only on the ’C30, is
4K 32 bits. Each RAM and ROM block is capable of supporting two CPU
accesses in a single cycle.
Figure 2–6 shows how the memory is organized on the ’C31. RAM blocks 0
and 1 are each 1K
32 bits and support two accesses in a single cycle. A boot
loader allows the loading of program and data at reset from 8-, 16-, 32-bit-wide
memories or serial port.
Figure 2–7 shows how the memory is organized on the ’C32. RAM blocks 0
and 1 are each 256
32 bits and support two accesses in a single cycle. A
boot loader allows the loading of program and data at reset from 1-, 2-, 4-, 8-,
16-, and 32-bit-wide memories or serial port. The ’C32 enhanced external
memory interface provides the flexibility to address 8-, 16-, or 32-bit data indepen-
dently of the external memory width. The external memory width can be 8-, 16-,
or 32-bits wide.
The ’C3x’s separate program, data, and DMA buses allow for parallel program
fetches, data reads and writes, and DMA operations. For example, the CPU can
access two data values in one RAM block and perform an external program
fetch in parallel with the DMA controller loading another RAM block, all within
a single cycle.