Texas Instruments TMS320C3x - Manual (Page 555)

Decrement and Branch Conditionally (Delayed) DBcondD
13-97 Assembly Language Instructions
Syntax DB cond D ARn, src
Operation AR n – 1
→
AR n
If cond is true and ARn
≥
0:
If src is in register addressing mode (Rn, 0
≤
n
≤
27)
src
→
PC
If src is in PC-relative mode (label or address)
displacement + PC + 3
→
PC.
Else, continue
Operands src conditional-branch addressing modes (B):
0 register
1 PC relative
AR n register (0
≤
n
≤
7)
Opcode
31 24 23 16 8 7 0 15
0 1 1 0 1 1 B 1 cond Register or displacement AR n
Description DB cond D signifies a delayed branch that allows the three instructions after
the delayed branch to be fetched before the PC is modified. The effect is a
single-cycle branch. The specified auxiliary register is decremented, and a
branch is performed if the condition is true and the specified auxiliary register
is greater than or equal to 0. The condition flags are those set by the last pre-
vious instruction that affects the status bits. The three instructions following the
DB
cond D do not affect the condition.
The auxiliary register is treated as a 24-bit signed integer. The 8 MSBs are un-
modified by the decrement operation. The comparison of the auxiliary register
uses only the 24 LSBs of the auxiliary register. The branch condition does not
depend on the auxiliary register decrement.
If the src operand is expressed in register-addressing mode, the contents of
the specified register are loaded into the PC. If the src is expressed in PC-rela-
tive addressing, the assembler generates a displacement: displacement = la-
bel – (PC of branch instruction + 3). This displacement is added to the PC of
the branch instruction plus 3 to generate the new PC. Note that bit 21 = 1 for
a delayed branch.
The ’C3x provides 20 condition codes that you can use with this instruction
(see Table 13–12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Condition flags are set on a previous instruction only when
the destination register is one of the extended-precision registers (R7–R0) or
when one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB,
or TSTB3) is executed.