Texas Instruments TMS320C3x - Manual (Page 595)

Logical Shift LSH
13-137 Assembly Language Instructions
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 output is generated; 0 otherwise
V 0
C Set to the value of the last bit shifted out; 0 for a shift count of 0
OVM Operation is not affected by OVM bit value.
Example 1 LSH R4,R7
Before Instruction After Instruction
R4 00 0000 0018 R4 00 0000 0018
R7 00 0000 02AC R7 00 AC00 0000
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 1
Z 0 Z 0
V 0 V 1
C 0 C 0
24 24
Example 2 LSH *–AR5(IR1),R5
Before Instruction After Instruction
R5 00 12C0 0000 R5 00 0001 2C00
AR5 80 9908 AR5 80 9908
IR0 4 IR0 4
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
809904h 0FFFFFFF4 809904h 0FFFFFFF4 –12 –12
Mode Bit