Texas Instruments TMS320C3x - Manual (Page 343)

Bus Timing
10-40
Figure 10–23. Read-Read-Write Sequence for STRBx Active
RDY
D
A
R/W
STRBx
H1
H3
Read Read Write
Figure 10–24 shows a zero wait-state write-write-read sequence for STRBx
active. During back-to-back writes, the data is valid when STRBx changes for the
first write, but for subsequent writes the data is valid when the address changes.
Figure 10–24. Write-Write-Read Sequence for STRBx Active
RDY
D
A
R/W
STRBx
H1
H3
Write Write Read