Texas Instruments TMS320C3x - Manual (Page 669)

Repeat Single Instruction RPTS
13-211 Assembly Language Instructions
Syntax RPTS src
Operation src
→
RC
1
→
ST (RM)
1
→
S
Next PC
→
RS
Next PC
→
RE
Operands src general addressing modes (G):
0 0 register
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
Opcode
31 24 23 16 8 7 0 15
0 0 0 1 0 1 1 1 0 1 src G 1 1 1 0
Description The RPTS instruction allows you to repeat a single instruction src + 1 times
without any penalty for looping. Fetches can also be made from the instruction
register (IR), thus avoiding repeated memory access.
The src operand is loaded into the repeat counter (RC). A 1 is written into the
repeat mode bit of the status register ST (RM). A 1 is also written into the re-
peat single bit (S). This indicates that the program fetches are to be performed
only from the instruction register. The next PC is loaded into the repeat end-ad-
dress (RE) register and the repeat start-address (RS) register.
For the immediate mode, the src operand is assumed to be an unsigned inte-
ger and is not sign extended.
Cycles 4
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z
Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value. Mode Bit