Texas Instruments TMS320C3x - Manual (Page 69)

CPU Multiport Register File
3-6
Table 3–2. Status Register Bits
Bit Name Reset Value Name Description
C 0 Carry flag Carry condition flag
V 0 Overflow flag Overflow condition flag
Z 0 Zero flag Zero condition flag
N 0 Negative flag Negative condition flag
UF 0 Floating-point under-
flow flag Floating-point underflow condition flag
LV 0 Latched overflow flag Latched overflow condition flag
LUF 0 Latched floating-point
underflow flag Latched floating-point underflow condition flag
OVM 0 Overflow mode flag Overflow mode flag
The overflow mode flag affects only integer operations.
If OVM = 0, the overflow mode is turned off and integer
results that overflow are treated in no special way.
If OVM = 1, integer results overflowing in the positive
direction are set to the most positive, 2s-complement
number (7FFF FFFFh), and integer results overflowing
in the negative direction are set to the most negative
32-bit, 2s-complement number (8000 0000h).
RM 0 Repeat mode flag Repeat mode flag
If RM = 1, the PC is modified in either the repeat-block
or repeat-single mode.
CE 0 Cache enable CE enables or disables the instruction cache.
Set CE = 1 to enable the cache, allowing the cache to
be used according to the least recently used (LRU)
stack manipulation.
Set CE = 0 to disable the cache, preventing cache
updates or modifications (no cache fetches can be
made). Cache clearing (CC = 1) is allowed when
CE = 0.
Note: If a load of the status register occurs simultaneously with a CPU interrupt pulse trying to reset GIE, GIE is reset.