Texas Instruments TMS320C3x - Manual (Page 500)

ABSF||STF Parallel ABSF and STF
13-42
Syntax ABSF src2, dst1
|| STF src3, dst2
Operation | src2 |
→
dst1
|| src3
→
dst2
Operands src2 indirect ( disp = 0, 1, IR0, IR1)
dst1 register (R n1, 0
≤
n1
≤
7)
src3 register (R n2, 0
≤
n2
≤
7)
dst2 indirect ( disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
src2 indirect ( disp = 0, 1, IR0, IR1) or any CPU register
dst1 register (R n1, 0
≤
n1
≤
7)
src3 register (R n2, 0
≤
n2
≤
7)
dst2 indirect ( disp = 0, 1, IR0, IR1)
Opcode
31 24 23 16 8 7 0 15
1 1 0 0 1 0 dst1 src2 dst2 0 src3 0 0 0
Description A floating-point absolute value and a floating-point store are performed in paral-
lel. All registers are read at the beginning and loaded at the end of the execute
cycle. If one of the parallel operations (STF) reads from a register and the opera-
tion being performed in parallel (ABSF) writes to the same register, STF accepts
the contents of the register as input before it is modified by the ABSF.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
If src3 and dst1 point to the same register, src3 is read before the write to dst1.
An overflow occurs if src (man) = 80000000h and src (exp) = 7Fh. The result
is dst (man) = 7FFFFFFFh and dst (exp) = 7Fh.
Cycles 1
Status Bits LUF Unaffected
LV 1 if a floating-point overflow occurs; unchanged otherwise
UF 0
N 0
Z 1 if a 0 result is generated; 0 otherwise
V 1 if a floating-point overflow occurs; 0 otherwise
C Unaffected