Texas Instruments TMS320C3x - Manual (Page 639)

No Operation NOP
13-181 Assembly Language Instructions
Syntax NOP src
Operation No ALU or multiplier operations.
AR
n is modified if src is specified in indirect mode.
Operands src general addressing modes (G):
0 0 register(no operation)
1 0 indirect (modify AR n, 0
≤
n
≤
7)
(disp = 0–255, IR0, IR1)
Opcode
31 24 23 16 8 7 0 15
0 0 0 0 1 0 0 1 1 src G 0 0 0 0 0
Description If the src operand is specified in the indirect mode, the specified addressing
operation is performed, and a dummy memory read occurs. If the src operand
is omitted, no operation is performed.
Cycles 1
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.
Example 1 NOP
Before Instruction After Instruction
PC 3A PC 3B
Example 2 NOP *AR3 – – (1)
Before Instruction After Instruction
AR3 80 9900 AR3 80 98FF
PC 5 PC 6
Mode Bit