Texas Instruments TMS320C3x User Manual
Page 581
Load Integer
LDI
13-123
Assembly Language Instructions
Syntax
LDI
src, dst
Operation
src
→
dst
Operands
src general addressing modes (G):
0 0
any CPU register
0 1
direct
1 0
indirect (disp = 0–255, IR0, IR1)
1 1
immediate
dst any CPU register
Opcode
31
24 23
16
8 7
0
15
0 0 0
0 1
0
0
0
0
dst
src
G
Description
The
src operand is loaded into the dst register. The dst and src operands are
assumed to be signed integers. An alternate form of LDI, LDP, is used to load
the data-page pointer register (DP). See the LDP instruction in Section 13.6.2
Optional Assembler Syntax beginning on page 13-34.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 – R0.
LUF
Unaffected
LV
Unaffected
UF
0
N
1 if a negative result is generated; 0 otherwise
Z
1 if a 0 result is generated; 0 otherwise
V
0
C
Unaffected
OVM
Operation is not affected by OVM bit value.
Mode Bit