Texas Instruments TMS320C3x - Manual (Page 433)

DMA Controller
12-54
Table 12–6. DMA Global-Control Register Bits Summary
Abbreviation
Reset
Value Name Description
START 00 DMA start control Controls the state in which the DMA starts and stops. The
DMA may be stopped without any loss of data.
The following table summarizes the START bits and DMA
operation:
Bit 1 Bit 0 Function
0 0 DMA read or write cycles in progress are
completed; any data read is ignored. Any
pending read or write is cancelled. The
DMA is reset so that when it starts, a new
transaction begins; that
is, a read is per-
formed (Reset value).
0 1 If a read or write has begun, it is completed
before it stops. If a read or write has not
begun, no
read or write is started.
1 0 If a DMA transfer has begun, the entire
transfer
is complete (including both read
and write operations) before stopping. If a
transfer has not begun,
none is started.
1 1 DMA starts from reset or restarts from the
previous state.
When the DMA completes a transfer, the START bits remain
in 11 (base 2). The DMA starts when the START bits are set
to 11 and one of the following conditions applies:
- The transfer counter is set to a value different from 0x0.
- The TC bit is set to 0.
STAT 00 DMA status Indicates the status of the DMA and changes every cycle.
The following table summarizes the STAT bits and DMA status.
Bit 3 Bit 2 Function
0 0 The DMA is being held between DMA
transfer
(between a write and a read). This
is the value at reset.
0 1 DMA is being held in the middle of a DMA
transfer
(between a read and a write).
1 0 Reserved.
1 1 DMA busy. DMA is performing a read or
write
or waiting for a source or destination
synchronization interrupt.