Texas Instruments TMS320C3x - Manual (Page 44)

Central Processing Unit (CPU)
2-8
2.2.1 Floating-Point/Integer Multiplier
The multiplier performs single-cycle multiplications on 24-bit integer and 32-bit
floating-point values. The ’C3x implementation of floating-point arithmetic allows
for floating-point or fixed-point operations at speeds up to 33-ns per instruction
cycle. To gain even higher throughput, you can use parallel instructions to perform
a multiply and an ALU operation in a single cycle.
When the multiplier performs floating-point multiplication, the inputs are 32-bit
floating-point numbers, and the result is a 40-bit floating-point number. When
the multiplier performs integer multiplication, the input data is 24 bits and yields
a 32-bit result. See Chapter 5,
Data Formats and Floating-Point Operation, for
detailed information.
2.2.2 Arithmetic Logic Unit (ALU) and Internal Buses
The ALU performs single-cycle operations on 32-bit integer, 32-bit logical,
and 40-bit floating-point data, including single-cycle integer and floating-
point conversions. Results of the ALU are always maintained in 32-bit integer
or 40-bit floating-point formats. The barrel shifter is used to shift up to 32 bits
left or right in a single cycle. See Chapter 5,
Data Formats and Floating-Point
Operation, for detailed information.
Four internal buses, CPU1, CPU2, REG1, and REG2 carry two operands from
memory and two operands from the register file, allowing parallel multiplies
and adds/subtracts on four integer or floating-point operands in a single cycle.
2.2.3 Auxiliary Register Arithmetic Units (ARAUs)
Two auxiliary register arithmetic units (ARAU0 and ARAU1) can generate two
addresses in a single cycle. The ARAUs operate in parallel with the multiplier
and ALU. They support addressing with displacements, index registers (IR0 and
IR1), and circular and bit-reversed addressing. See Chapter 6,
Addressing
Modes, for more information.