Texas Instruments TMS320C3x - Manual (Page 228)

DMA Interrupts
7-44
7.7.5 TMS320C30 Interrupt Considerations
The ’C30 silicon revisions earlier than 4.0 have two unique exceptions to the
interrupt operation. This does not apply to ’C30 silicon revision 4.0 or greater,
any ’C31 silicon, or any ’C32 silicon.
On ’C30 silicon revisions earlier than 4.0:
- The status register global interrupt-enable (GIE) bit may be erroneously
reset to 0 (disabled setting) if all of the following conditions are true:
J A conditional trap instruction (TRAP cond) has been fetched
J The condition for the trap is false.
J A pipeline conflict has occurred, resulting in a delay in the decode or
read phase of the instruction.
During the decode phase of a conditional trap, interrupts are temporarily
disabled to ensure that the trap executes before a subsequent interrupt. If a
pipeline conflict occurs and causes a delay in execution of the conditional
trap, the interrupt disabled condition may become the last known condition of
the GIE bit. If the trap condition is
false, interrupts are permanently disabled
until the GIE bit is intentionally set. The condition is not present when the trap
condition is
true, because normal operation of the instruction causes the GIE
to be reset, and standard coding practice sets the GIE to 1 before the trap
routine is exited. Several instruction sequences that cause pipeline conflicts
have been found:
J
LDI mem,SP
TRAPcond n
J
LDI mem,SP
NOP
TRAPcond n
J
STI SP,mem
TRAPcond n
J
STI Rx,*ARy
LDI *ARx,Ry
||LDI *ARz,Rw
TRAPcond n
Other similar conditions may also cause a delay in the execution. The
following solution is recommended to avoid or rectify the problem: