Texas Instruments TMS320C3x - Manual (Page 615)

Parallel MPYF3 and SUBF3 MPYF3||SUBF3
13-157 Assembly Language Instructions
Opcode
31 24 23 16 8 7 0 15
1 0 0 0 0 1 src4 src3 P src1 src2 d1 d2
Description A floating-point multiplication and a floating-point subtraction are performed
in parallel. All registers are read at the beginning and loaded at the end of the
execute cycle. If one of the parallel operations (MPYF3) reads from a register
and the operation being performed in parallel (SUBF3) writes to the same reg-
ister, MPYF3 accepts as input the contents of the register before it is modified
by the SUBF3.
Any combination of addressing modes can be coded for the four possible
source operands as long as two are coded as indirect and two are coded regis-
ter. The assignment of the source operands
srcA – srcD to the src1 – src4
fields varies, depending on the combination of addressing modes used, and
the P field is encoded accordingly.
Cycles 1
Note: Cycle Count
One cycle if:
- src3 and src4 are in internal memory
- src3 is in internal memory and src4 is in external memory
Two cycles if:
- src3 is in external memory and src4 is in internal memory
- src3 and src4 are in external memory
For more information see Section 8.5, Clocking Memory Accesses, on page
8-24.