Texas Instruments TMS320C3x - Manual (Page 410)

Serial Ports
12-31 Peripherals
Figure 12–22. Serial-Port Clocking in Serial-Port Mode
CLKX FUNC= 1 (serial-port mode)
CLKX I/O
= 1 (output serial-port CLK)
XCLK SRC = 0 or 1
(a)
TSTAT
TSTAT
TSTAT
Timer Timer
Timer
XSR XSR
XSR
Internal
CLKX
CLKX
CLKX
INV
INV
INV
Internal
clock Internal
clock
DATOUT (NC)
DATIN
DATOUT (NC)
DATIN
DATOUT (NC)
DATIN
CLKX FUNC= 1 (serial-port mode)
CLKX I/O
= 0 (input serial-port CLK)
XCLK SRC = 1 (internal CLK for timer)
(b)
CLKX FUNC= 1 (serial-port mode)
CLKX I/O
= 0 (input serial-port CLK)
XCLK SRC = 0 (external CLK for timer)
(c)
External Internal External
Internal External
12.2.10 Serial-Port Timing
The formula for calculating the frequency of the serial-port clock with an inter-
nally generated clock depends upon the operation mode of the serial-port
timers, defined as:
f (pulse mode) = f (timer clock)/period register
f (clock mode) = f (timer clock)/(2 x period register)
An internally generated clock source f (timer clock) has a maximum frequency
of f(H1)/2. An externally generated serial-port clock f (timer clock) (CLKX or
CLKR) has a maximum frequency of less than f(H1)/2.6. See section 12.1.5
on page 12-7 for information on timer pulse/clock generation.
Transmit data is clocked out on the rising edge of the selected serial-port clock.
Receive data is latched into the receive-shift register on the falling edge of the
serial-port clock. All data is received MSB first and shifted to the left. If fewer than
32 bits are received, the data received is right-justified in the receive buffer.