Texas Instruments TMS320C3x - Manual (Page 443)

DMA Controller
12-64
Table 12–8.TMS320C32 DMA PRI Bits and CPU/DMA Arbitration Rules
DMA PRI
(Bits 13–12) Description
0 0 DMA access is lower priority than the CPU access. If the DMA
channel and the CPU request the same resource, then the CPU
has priority. (DMA PRI bits are set to 00
2
at reset.)
0 1 This setting selects rotating arbitration, which sets priorities between
the CPU and DMA channel by alternating their accesses, but not
exactly equally. Priority rotates between CPU and DMA accesses
when they conflict during
consecutive instruction cycles. The first
time the DMA channel and the CPU request the same resource,
the CPU has priority. If, in the following instruction cycle, the DMA
controller and the CPU again request the same resource, the DMA
has priority. Alternate access continues as long as the CPU and
DMA requests conflict in consecutive instruction cycles. When
there is no conflict in a previous instruction cycle, the CPU has
priority.
1 0 Reserved
1 1 DMA access is higher priority than the CPU access. If the DMA
channel and the CPU request the same resource, the DMA has
priority.
12.3.7 DMA and Interrupts
The DMA controller uses interrupts in the following way:
- It can send interrupts to the CPU or other DMA channel when a block
transfer finishes. See the TCINT bit field in the DMA global-control register
(Figure 12–36, Figure 12–37, or Figure 12–38 on page 12-53). The
EDINT bit field (’C30 and ’C31) or the EDINT0 and EDINT1 bit fields (’C32)
in the interrupt-enable register must be set to allow the CPU to be inter-
rupted by the DMA.
- It can receive interrupts from the external interrupt pins (INT3 – 0), the
timers, the serial ports, or other DMA channel.
This section explains how the DMA receives interrupts. This process is called
synchronization.
All of the interrupts that the DMA controller receives are detected by the CPU
interrupt controller and latched by the CPU in the appropriate interrupt-flag
register.