Texas Instruments TMS320C3x - Manual (Page 470)

Instruction Set Summary
13-12
Table 13–8. Instruction Set Summary (Continued)
Mnemonic Operation Description
DB cond Decrement and branch conditionally
(standard)
AR n – 1
→
AR n
If cond = true and ARn
≥
0:
If C src is a register, Csrc
→
PC
If C src is a value, Csrc + PC + 1
→
PC
Else, PC + 1
→
PC
DB condD Decrement and branch conditionally
(delayed) AR n – 1
→
AR n
If cond = true and ARn
≥
0:
If C src is a register, Csrc
→
PC
If C src is a value, Csrc + PC + 3
→
PC
Else, PC + 1
→
PC
FIX Convert floating-point value to integer Fix ( src)
→
Dreg
FLOAT Convert integer to floating-point value Float( src)
→
R n
IACK Interrupt acknowledge Dummy read of src
IACK toggled low, then high
IDLE Idle until interrupt PC + 1
→
PC
Idle until next interrupt
IDLE2 Low-power idle Idle until next interrupt stopping internal clocks
LDE Load floating-point exponent src(exponent)
→
R n(exponent)
LDF Load floating-point value src
→
R n
LDF cond Load floating-point value conditionally If cond = true, src
→
R n
Else, R n is not changed
LDFI Load floating-point value, interlocked Signal interlocked operation src
→
R n
LDI Load integer src
→
Dreg
Legend: AR n auxiliary register n (AR7–AR0) RE repeat interrupt register
C carry bit RM repeat mode bit
C src conditional-branch addressing modes R n register address (R7–R0)
count shift value (general addressing modes) RS repeat start register
cond condition code SP stack pointer
Daddr destination memory address Sreg register address (any register)
Dreg register address (any register) ST status register
GIE global interrupt enable register src general addressing modes
N any trap vector 0–27 src1 3-operand addressing modes
PC program counter src2 3-operand addressing modes
RC repeat counter register TOS top of stack