Texas Instruments TMS320C3x - Manual (Page 741)

Glossary
D-8
W
wait state: A period of time that the CPU must wait for external program,
data, or I/O memory to respond when it reads from or writes to that exter-
nal memory. The CPU waits one extra cycle for every wait state.
wait-state generator: A program that can be modified to generate a limited
number of wait states for a given off-chip memory space (lower program,
upper program, data, or I/O).
X
XA0–XA13: External address pin s for data/program memory or I/O devices.
These pins are on the expansion bus of the ’C30. See also A0–A23.
XD0–XD31: External data bus pins that transfer data between the processor
and external data/program memory or I/O devices of the ’C30. See also
D0–D31.
Z
zero fill: The process of filling the low- or high-order bits with 0s when load-
ing a number into a larger field.