Texas Instruments TMS320C3x - Manual (Page 371)

TMS320C32 Boot Loader
11-16
4) Otherwise, the boot loader attempts a memory boot load. Figure 11–6
shows the boot-loader memory flow. If the IF register’s INT0 bit field is set,
the source program is loaded from memory location 1000h. If the IF regis-
ter’s INT1 bit field is set, the source program is loaded from memory location
810000h. If the IF register’s INT2 bit field is set, the source program is
loaded from memory location 900000h. After determining the memory loca-
tion of the source program, the boot loader checks INT3 bit field in the IF
register. If this bit is set, all data transfers are performed with synchronous
handshake. The handshake protocol uses XF0 as a data-acknowledge and
XF1 as a data-ready signals. ’C32’s XF0 is an output pin while the XF1 is
an input pin. Figure 11–7 shows the handshake data-transfer operation.
The data-transfer operation occurs as follows:
a) The ’C32 boot loader waits until the host sets XF1 low to read in the
data. While the ’C32 waits for XF1 to drop low, the IACK pin pulses
until XF1 is low. Setting XF1 low communicates to the ’C32 that the
data is valid. The IACK pulse indicates that the ’C32 is waiting for data.
b) The boot loader sets XF0 low after reading the data value. Dropping
XF0 acknowledges to the host that the data was read.
c) The host sets XF1 high to inform the ’C32 that the data is no longer valid.
d) The ’C32 terminates the transfer by setting XF0 high.
The memory boot-load source program has a header indicating the boot
memory width and the contents of the STRB0, STRB1, and IOSTRB control
registers (see Table 11–2).
5) After reading the header, the boot loader copies the source-program
blocks. The source-program blocks have three entries preceding the
source-program-block data. The first entry in the source-program block
indicates the size of the block, the second entry indicates the address where
the block is to be loaded, while the third entry contains the destination-
memory strobe including a pointer that identifies the destination-memory
strobe (STRB0, STRB1, or IOSTRB) and a value that describes the strobe
configuration for the memory width and data-type size. If the destination
memory is internal, the third entry should contain a zero. The boot loader
cannot load the source program to any memory address below 1000h,
unless the address decode logic is remapped.
6) Once all the program blocks are loaded into their respective address loca-
tions with the given data-type sizes, the boot loader sets the IOSTRB,
STRB0, and STRB1 control registers to the values read at the beginning
of the boot-load process.
7) The boot loader branches to the destination address of the first source
block loaded and begins program execution.