Texas Instruments TMS320C3x - Manual (Page 476)

Parallel Instruction Set Summary
13-18
Table 13–9. Parallel Instruction Set Summary (Continued)
(a) Parallel arithmetic with store instructions (Continued)
Mnemonic Description Operation
LDF
|| STF
Load floating-point value src2
→
dst1
|| src3
→
dst2
LDI
|| STI
Load integer src2
→
dst1
|| src3
→
dst2
LSH3
|| STI
Logical shift If count
≥
0:
src2 << count
→
dst1
|| src3
→
dst2
Else:
src2 >> |count|
→
dst1
|| src3
→
dst2
MPYF3
|| STF
Multiply floating-point value src1 x src2
→
dst1
|| src3
→
dst2
MPYI3
|| STI
Multiply integer src1 x src2
→
dst1
|| src3
→
dst2
NEGF
|| STF
Negate floating-point value 0 – src2
→
dst1
|| src3
→
dst2
NEGI
|| STI
Negate integer 0 – src2
→
dst1
|| src3
→
dst2
NOT
|| STI
Complement src1
→
dst1
|| src3
→
dst2
OR3
|| STI
Bitwise-logical OR src1 OR src2
→
dst1
|| src3
→
dst2
STF
|| STF
Store floating-point value src1
→
dst1
|| src3
→
dst2
STI
|| STI
Store integer src1
→
dst1
|| src3
→
dst2
Legend: count register addr (R7–R0) op3 register addr (R0 or R1)
dst1 register addr (R7–R0) op6 register addr (R2 or R3)
dst2 indirect addr ( disp = 0, 1, IR0, IR1) src1 register addr (R7–R0)
op1, op2, op4, and op5 src2 indirect addr ( disp = 0, 1, IR0, IR1)
Any two of these operands must be src3 register addr (R7–R0)
specified using register addr; the remaining
two must be specified using indirect.