Texas Instruments TMS320C3x - Manual (Page 426)

Serial Ports
12-47 Peripherals
4) The bit clock drives both the A/D’s and D/A’s XCLK input.
5) The ’C3x transmit clock also acts as the input clock on the receive side of
the ’C3x serial port.
6) Since the receive clock is synchronous to the internal clock of the ’C3x, the
receive clock can run at full speed (that is, f(H1)/2).
Similarly, on receiving a convert command, the pipelined D/A converts the last
word received from the ’C3x and signals the ’C3x via the SYNC signal (connected
to the ’C3x FSX0 pin) to begin transmitting a 32-bit word representing the two
channels of data to be converted. The data transmitted from the ’C3x DX0 pin is
input to both the SINA and SINB inputs of the D/A as shown in Example 12–7.
The ’C3x is set up to transfer bits at the maximum rate of about 8 Mbps, with a
dual-channel sample rate of about 44.1 kHz. Assuming a 32-MHz CLKIN, you
can configure this standard-mode fixed-data-rate signaling interface by setting
the registers as described below:
Serial Port:
Port global-control register
0EBC0040h
FSX/DX/CLKX port-control register 00000111h
FSR/DR/CLKR port-control register 00000111h
Receive/transmit timer-control register 0000000Fh
Timer:
Timer global-control register
000002C1h
Timer-period register 000000B5h