And3||sti – Texas Instruments TMS320C3x User Manual
Page 523
Parallel AND3 and STI
AND3||STI
13-65
Assembly Language Instructions
Syntax
AND3
src2, src1, dst1
STI
src3, dst2
Operation
src1 AND src2
→
dst1
||
src3
→
dst2
Operands
src1
register (R
n1, 0
≤
n1
≤
7)
src2
indirect (
disp = 0, 1, IR0, IR1)
dst1
register (R
n2, 0
≤
n2
≤
7)
src3
register (R
n3, 0
≤
n3
≤
7)
dst2
indirect (
disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
-
’C31 silicon revision 6.0 or greater
-
’C32 silicon revision 2.0 or greater
src1
register (R
n1, 0
≤
n1
≤
7)
src2
indirect (
disp = 0, 1, IR0, IR1) or any CPU register
dst1
register (R
n2, 0
≤
n2
≤
7)
src3
register (R
n3, 0
≤
n3
≤
7)
dst2
indirect (
disp = 0, 1, IR0, IR1)
Opcode
31
24 23
16
8 7
0
15
1 1 0 1 0 0 0
dst1
src1
src3
dst2
src2
Description
A bitwise-logical AND and an integer store are performed in parallel. All regis-
ters are read at the beginning and loaded at the end of the execute cycle. If
one of the parallel operations (STI) reads from a register and the operation be-
ing performed in parallel (AND3) writes to the same register, STI accepts the
contents of the register as input before it is modified by the AND3.
If
src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 – R0.
LUF
Unaffected
LV
Unaffected
UF
0
N
MSB of the output
Z
1 if a 0 result is generated; 0 otherwise
V
0
C
Unaffected