Texas Instruments TMS320C3x - Manual (Page 596)

LSH3 Logical Shift, 3-Operand
13-138
Syntax LSH3 count, src, dst
Operation If count
≥
0:
src << count
→
dst
Else:
src >> |count |
→
dst
Operands src 3-operand addressing modes (T):
0 0 any CPU register
0 1 indirect ( disp = 0, 1, IR0, IR1)
1 0 any CPU register
1 1 indirect ( disp = 0, 1, IR0, IR1)
count 3-operand addressing modes (T):
0 0 any CPU register
0 1 any CPU register
1 0 indirect ( disp = 0, 1, IR0, IR1)
1 1 indirect ( disp = 0, 1, IR0, IR1)
dst register (Rn, 0
≤
n
≤
27)
Opcode
31 24 23 16 8 7 0 15
0 0 1 0 0 0 0 0 1 dst src T count
Description The seven LSBs of the count operand are used to generate the 2s-comple-
ment shift count.
If the count operand is greater than 0, a copy of the src operand is left shifted
by the value of the count operand, and the result is written to the dst. (The src
is not changed.) Low-order bits shifted in are zero filled, and high-order bits are
shifted out through the carry (C) bit.
Logical left shift:
C
←
src
←
0
If the count operand is less than 0, the src operand is right shifted by the abso-
lute value of the count operand. The high-order bits of the dst operand are 0-
filled as they are shifted to the right. Low-order bits are shifted out through the
C bit.
Logical right shift:
0
→
src
→
C
If the count operand is 0, no shift is performed, and the C bit is set to 0. The
count operand is assumed to be a signed integer. The src and dst operands
are assumed to be unsigned integers.