Texas Instruments TMS320C3x - Manual (Page 214)

Interrupts
7-30
Table 7–6. Interrupt and Trap-Vector Locations for the TMS320C32
Address Name Function
EA[ITTP] + 00h Reserved
EA[ITTP] + 01h INT0 External interrupt on the INT0 pin
EA[ITTP] + 02h INT1 External interrupt on the INT1 pin
EA[ITTP] + 03h INT2 External interrupt on the INT2 pin
EA[ITTP] + 04h INT3 External interrupt on the INT3 pin
EA[ITTP] + 05h XINT0 Internal interrupt generated when serial port 0 transmit buffer
is empty
EA[ITTP] + 06h RINT0 Internal interrupt generated when serial port 0 transmit buffer
is full
EA[ITTP] + 07h Reserved
EA[ITTP] + 08h Reserved
EA[ITTP] + 09h TINT0 Internal interrupt generated by timer0
EA[ITTP] + 0Ah TINT1 Internal interrupt generated by timer1
EA[ITTP] + 0Bh DINT0 Internal interrupt generated by DMA channel 0
EA[ITTP] + 0Ch DINT1 Internal interrupt generated by DMA channel 1
EA[ITTP] + 0Dh Reserved
EA[ITTP] + 1Fh Reserved
EA[ITTP] + 20h TRAP 0 Internal interrupt generated by TRAP 0 instruction
•
•
•
EA[ITTP] + 3Bh TRAP 27 Internal interrupt generated by TRAP 27 instruction
EA[ITTP] + 3Ch TRAP 28 (reserved)
EA[ITTP] + 3Dh TRAP 29 (reserved)
EA[ITTP] + 3Eh TRAP 30 (reserved)
EA[ITTP] + 3Fh TRAP 31 (reserved)