Texas Instruments TMS320C3x - Manual (Page 541)

Branch Unconditionally (Standard) BR
13-83 Assembly Language Instructions
Syntax BR src
Operation src
→
PC
Operands src long-immediate addressing mode
Opcode
31 24 23 16 8 7 0 15
0 1 1 0 0 0 0 0 src
Description BR performs a PC-relative branch that executes in four cycles, since a pipeline
flush also occurs upon execution of the branch (see Section 8.2,
Pipeline Con-
flicts, on page 8-4). An unconditional branch is performed. The src operand is
assumed to be a 24-bit unsigned integer. Note that bit 24 = 0 for a standard
branch.
Cycles 4
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.
Example BR 805Ch
Before Instruction After Instruction
PC 0080 PC 805C
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Mode Bit