Addi3 – Texas Instruments TMS320C3x User Manual
Page 516
ADDI3
Add Integer, 3-Operand
13-58
Syntax
ADDI3
<src2 >,<src1 >,<dst >
Operation
src1 + src2
→
dst
Operands
src1 3-operand addressing modes (T):
0 0
any CPU register
0 1
indirect (
disp = 0, 1, IR0, IR1)
1 0
any CPU register
1 1
indirect (
disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
0 0
any CPU register
0 1
any CPU register
1 0
indirect (
disp = 0, 1, IR0, IR1)
1 1
indirect (
disp = 0, 1, IR0, IR1)
dst any CPU register
Opcode
31
24 23
16
8 7
0
15
0 0 1 0 0 0
0
T
src2
dst
src1
1
0
Description
The sum of the
src1 and src2 operands is loaded into the dst register. The src1,
src2, and dst operands are assumed to be signed integers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 – R0.
LUF
Unaffected
LV
1 if an integer overflow occurs; unchanged otherwise
UF
0
N
1 if a negative result is generated; 0 otherwise
Z
1 if a 0 result is generated; 0 otherwise
V
1 if an integer overflow occurs; 0 otherwise
C
1 if a carry occurs; 0 otherwise
OVM
Operation is affected by OVM bit value.
Mode Bit