Texas Instruments TMS320C3x - Manual (Page 444)

DMA Controller
12-65 Peripherals
The DMA and the CPU can respond to the same interrupt if the CPU is not
involved in any pipeline conflict or in any instruction that halts instruction fetching.
Refer to section 7.6.2,
Interrupt Vector Table and Prioritization, on page 7-29 for
more details. It is also possible for different DMA channels to respond to the same
interrupt. If the same interrupt is selected for source and destination synchroniza-
tion, both read and write cycles are enabled with a single incoming interrupt.
12.3.7.1 Interrupts and Synchronization of DMA Channels
You can use interrupts to synchronize DMA channels. This section describes
the following four synchronization mechanisms:
- No synchronization (SYNC = 0 0)
When SYNC = 0 0, no synchronization is performed. The DMA performs
reads and writes whenever there are no conflicts. All interrupts are ignored
and are considered to be globally disabled. However, no bits in the DMA
interrupt-enable register are changed. Figure 12–43 shows the synchro-
nization mechanism when SYNC = 0 0.
Figure 12–43. Mechanism for No DMA Synchronization
Start
DMA channel performs a read
DMA channel performs a write
Go to start
- Source synchronization (SYNC = 0 1)
When SYNC = 0 1, the DMA is synchronized to the source (see
Figure 12–44). A read is not performed until an interrupt is received by the
DMA. Then all DMA interrupts are disabled globally. However, no bits in
the DMA interrupt-enable register are changed.