Texas Instruments TMS320C3x - Manual (Page 522)

AND3 Bitwise-Logical AND, 3-Operand
13-64
Example 1 AND3 *AR0 – – (IR0),*+AR1,R4
Before Instruction After Instruction
R4 00 0000 0000 R4 00 0000 0020
AR0 80 98F4 AR0 80 98A4
AR1 80 9951 AR1 80 9951
IR0 50 IR0 50
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
8098F4h 30 8098F4h 30
809952h 123 809952h 123
Example 2 AND3 *–AR5,R7,R4
Before Instruction After Instruction
R4 00 0000 0000 R4 00 0000 0002
R7 00 0000 0002 R7 00 0000 0002
AR5 80 985C AR5 80 985C
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
80985Bh 0AFF 80985Bh 0AFF
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.