Texas Instruments TMS320C3x - Manual (Page 448)

DMA
Controller
12-69
Peripherals
Figure 12–47. DMA Timing When Destination is On Chip
Cycles (H1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate
Source on chip R1 R2 R3 R4 R5 R6 R7 R8
(1 + 1) T
Destination on chip W1 W2 W3 W4 W5 W6 W7
(1 + 1) T
Source STRB STRB0 STRB1 MSTRB bus
R1 R1 R1 I R2 R2 R2 I R3 R3 R3 I
Source STRB, STRB0, STRB1, MSTRB bus
Cr Cr Cr (2 + Cr +1) T
Destination on chip W1 W2 W3
Source IOSTRB bus
R1 R1 R1 R1 I R2 R2 R2 R2 I R3 R3 R3 R3 I
Source IOSTRB bus
Cr Cr Cr (3 + Cr + 1) T
Destination on chip W1 W2 W3
Legend:
T = Number of transfers W = Single-cycle writes
Cr = Source-read wait states R n = Multicycle reads
Cw = Destination-write wait states W n = Multicycle writes
R = Single-cycle reads I = Internal register cycle