Texas Instruments TMS320C3x - Manual (Page 422)

Serial Ports
12-43 Peripherals
Example 12–4 and Example 12–5 are serial-port register setups for the above
case. (Assume two ’C3xs have the same system clock.)
Example 12–4. Serial-Port Register Setup #1
Global control = 0EBC0064h; 32 bits, fixed data rate, burst mode,
Transmit port control = 0111h ; FSX (output), CLKX (output) = F(CLKIN)/8
Receive port control = 0111h ; CLKR (input), handshake mode, transmit
S_port timer control = 0Fh ; and receive interrupt is enabled.
S_port timer count = 0h
S_port timer period
≥
01h
Example 12–5. Serial-Port Register Setup #2
Global control = 0C000364h; 8 bits, variable data rate, burst mode,
Transmit port control = 0111h; FSX (output), CLKX (output) = f(CLKIN)/24
Receive port control = 0111h ; CLKR (input), handshake mode, transmit
S_port timer control = 0Fh ; and receive interrupt is disabled.
S_port timer count = 0h
S_port timer period ≥ 01h
Since the data has a leading 1 and the acknowledge signal is a 0 in the hand-
shake mode, the ’C3x serial port can distinguish between the data and the
acknowledge signal. Even if the ’C3x serial port receives the data before the
acknowledge signal, the data is not misinterpreted as the acknowledge signal
and lost. Additionally, the acknowledge signal is not generated until the data
is read from the data-receive register (DRR); the ’C3x does not transmit the
data and the acknowledge signal simultaneously.
12.2.14.2 CPU Transfer With Serial Port Transmit Polling Method
Example 12–6 sets up the CPU to transfer data (128 words) from an array buffer
to the serial port 0 output register when the previous value stored in the serial-
port output register has been sent. Serial port 0 is initialized to transmit 32-bit
data words with an internally generated frame sync and a bit-transfer rate of
8H1 cycles/bit.