Texas Instruments TMS320C3x - Manual (Page 715)

Instruction Opcodes
A-4
Table A–1. TMS320C3x Instruction Opcodes (Continued)
Instruction 23 24 25 26 27 28 29 30 31
SUBRB 0 0 0 1 1 0 0 0 1
SUBRF 0 0 0 1 1 0 0 1 0
SUBRI 0 0 0 1 1 0 0 1 1
TSTB 0 0 0 1 1 0 1 0 0
XOR 0 0 0 1 1 0 1 0 1
IACK 0 0 0 1 1 0 1 1 0
ADDC3 0 0 1 0 0 0 0 0 0
ADDF3 0 0 1 0 0 0 0 0 1
ADDI3 0 0 1 0 0 0 0 1 0
AND3 0 0 1 0 0 0 0 1 1
ANDN3 0 0 1 0 0 0 1 0 0
ASH3 0 0 1 0 0 0 1 0 1
CMPF3 0 0 1 0 0 0 1 1 0
CMPI3 0 0 1 0 0 0 1 1 1
LSH3 0 0 1 0 0 1 0 0 0
MPYF3 0 0 1 0 0 1 0 0 1
MPYI3 0 0 1 0 0 1 0 1 0
OR3 0 0 1 0 0 1 0 1 1
SUBB3 0 0 1 0 0 1 1 0 0
SUBF3 0 0 1 0 0 1 1 0 1
SUB13 0 0 1 0 0 1 1 1 0
TSTB3 0 0 1 0 0 1 1 1 1
XOR3 0 0 1 0 1 0 0 0 0
LDF cond 0 1 0 0 – – – – –
LDI cond 0 1 0 1 – – – – –
BR(D) † 0 1 1 0 0 0 0 – –
CALL 0 1 1 0 0 0 1 – –
† The opcode is the same for standard and delayed instructions.