Texas Instruments TMS320C3x - Manual (Page 265)

Clocking Memory Accesses
8-29 Pipeline Operation
8.5.2.3 Operations with Parallel Stores
The next class of instructions includes every instruction that has a store in parallel
with another instruction. Bits 31 and 30 for these instructions are equal to 1 1.
The instruction word format for operations that perform a multiply or ALU opera-
tion in parallel with a store is shown in Figure 8–5. If the store operation to
dst2
is external or internal, it is performed during H3. Two bus cycles are required for
external stores, but only one CPU cycle is necessary to complete the write.
If the memory read operation is external, it starts at the beginning of H3 and
latches at the end of H1. If the memory read operation is internal, it is
performed during H1. Note that memory reads are performed by the CPU
during the read (R) phase of the pipeline, and stores are performed during the
execute (E) phase.
Figure 8–5. Multiply or CPU Operation With a Parallel Store
31
1 1 Operation src1 d1 src4
24 23 16 15 8 7 0
P d2 src2 src3
The instruction word format for instructions that have parallel stores to memory
is shown in Figure 8–6. If both destination operands,
dst1 and dst2, are located
in internal memory, dst1 is stored during H3 and dst2 during H1, thus completing
two memory stores in a single cycle.
Figure 8–6. Two Parallel Stores
31
1 1 src2 dst2
24 23 16 15 8 7 0
src1 dst1 ST||ST 0 0 0
- If dst1 is in external memory and dst2 is in internal memory, the dst1 store
begins at the start of H3. The dst2 store to internal memory is performed
during H1. Two bus cycles are required for the external store, but only one
CPU cycle is necessary to complete the write. Again, two memory stores
are completed in a single cycle.
- If dst1 is in internal memory and dst2 is in external memory, an additional bus
cycle is necessary to complete the dst2 store. Only one CPU cycle is neces-
sary to complete the write, but the port access requires three bus cycles. In
the first cycle, the internal
dst1 store is performed during H3, and dst2 is writ-
ten to the port during H1. During the next cycle, the dst2 store is performed
on the external bus, beginning in H3, and executes as normal through the
following cycle.