Texas Instruments TMS320C3x - Manual (Page 216)

Interrupts
7-32
7.6.4 CPU Interrupt Control Bits
Three CPU registers contain bits that control interrupt operation:
- Status (ST) register
The CPU global interrupt-enable bit (GIE) located in the CPU status register
(ST) controls all maskable CPU interrupts. When this bit is set to 1, the CPU
responds to an enabled interrupt. When this bit is cleared to 0, all CPU inter-
rupts are disabled. see Section 3.1.7 on page 3-5 for more information.
- CPU/DMA interrupt-enable (IE) register
This register individually enables/disables CPU, DMA external, serial port,
and timer interrupts. See Section 3.1.8 on page 3-9 for more information.
- CPU interrupt flag (IF) register
This register contains interrupt flag bits that indicate the corresponding
interrupt is set. See Section 3.1.9 on page 3-11 for more information.
7.6.5 Interrupt Flag Register Behavior
When an external interrupt occurs, the corresponding bit of the IF register is set
to 1. When the CPU or DMA controller processes this interrupt, the corresponding
interrupt flag bit is cleared by the internal interrupt acknowledge signal. However,
for level-triggered interrupts, if INT
n is still low when the interrupt acknowledge
signal occurs, the interrupt flag bit is cleared for only one cycle and then set again,
because INT
n is still low. Depending on when the IF register is read, it is also
possible that this bit may be 0 even though INT n is 0. When the ’C3x is reset,
0 is written to the interrupt flag register, clearing all pending interrupts.
The interrupt flag register bits can be read from and written to under software
control. Writing a 1 to an IF register bit sets the associated interrupt flag to 1.
Similarly, writing a 0 resets the corresponding interrupt flag to 0. In this way, all
interrupts may be triggered and/or cleared through software. Since the interrupt
flags may be read, the interrupt pins may be polled in software when an inter-
rupt-driven interface is not required.
Internal interrupts operate in a similar manner. In the IF register, the bit corre-
sponding to an internal interrupt can be read from and written to through software.
Writing a 1 sets the interrupt latch; writing a 0 clears it. All internal interrupts are
one H1/H3 cycle in length. If any previous bit value of the IF register needs to be
preserved, a modification to IF register should be performed with logic operations
(AND, OR, etc.) directly to IF.