Texas Instruments TMS320C3x - Manual (Page 386)

Timers
12-7 Peripherals
12.1.4 Timer-Period and Counter Registers
The 32-bit timer-period register is used to specify the frequency of the timer
signaling. The timer-counter register is a 32-bit register, which is reset to 0
whenever it increments to the value of the period register. Both registers are
set to 0 at reset.
Certain boundary conditions affect timer operation. These conditions are listed
below:
- When the period and counter registers are 0, the operation of the timer is
dependent upon the C/P mode selected. In pulse mode (C/P = 0), TSTAT
is set and remains set. In clock mode (C/P = 1), the width of the cycle is
2/f(H1), and the external clocks are ignored.
- When the counter register is not 0 and the period register = 0, the counter
counts, rolls over to 0, and behaves as described above.
- When the counter register is set to a value greater than the period register,
the counter may overflow when incremented. Once the counter reaches its
maximum 32-bit value (0FFFFFFFFh), it rolls over to 0 and continues.
Writes from the peripheral bus override register updates from the counter and
new status updates to the control register.
12.1.5 Timer Pulse Generation
The timer pulse generator (see Figure 12–1 on page 12-2) can generate several
external signals. You can invert these signals with the INV bit. The two basic
modes are pulse mode and clock mode, as shown in Figure 12–4. In both modes,
an internal clock source f (timer clock) has a frequency of f(H1)/2, and an external-
ly generated clock source f (timer clock) can have a maximum frequency of
f(H1)/2.6. In pulse mode (C/P = 0), the width of the pulse is 1/f(H1).