Ldf||stf – Texas Instruments TMS320C3x User Manual
Page 579
Parallel LDF and STF
LDF||STF
13-121
Assembly Language Instructions
Syntax
LDF
src2, dst1
||
STF
src3, dst2
Operation
src2
→
dst1
||
src3
→
dst2
Operands
src2
indirect (
disp = 0, 1, IR0, IR1)
dst1
register (R
n1, 0
≤
n1
≤
7)
src3
register (R
n2, 0
≤
n2
≤
7)
dst2
indirect (
disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented on the following devices:
-
’C31 silicon revision 6.0 or greater
-
’C32 silicon revision 2.0 or greater
src2
indirect (
disp = 0, 1, IR0, IR1) or any CPU register
dst1
register (R
n1, 0
≤
n1
≤
7)
src3
register (R
n2, 0
≤
n2
≤
7)
dst2
indirect (
disp = 0, 1, IR0, IR1)
Opcode
31
24 23
16
8 7
0
15
1 1 0 1 1 0
dst1
src2
dst2
0
0 0 0
src3
Description
A floating-point load and a floating-point store are performed in parallel.
If
src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles
1
Status Bits
LUF
Unaffected
LV
Unaffected
UF
Unaffected
N
Unaffected
Z
Unaffected
V
Unaffected
C
Unaffected
OVM
Operation is not affected by OVM bit value.
Mode Bit