Texas Instruments TMS320C3x - Manual (Page 599)

Parallel LSH3 and STI LSH3||STI
13-141 Assembly Language Instructions
Syntax LSH3 c ount, src2, dst1
|| STI src3, dst2
Operation If count
≥
0:
src2 << count
→
dst1
Else:
src2 >> |count |
→
dst1
|| src3
→
dst2
Operands count register (Rn1, 0
≤
n1
≤
7)
src1 indirect ( disp = 0, 1, IR0, IR1)
dst1 register (R n3, 0
≤
n3
≤
7)
src2 register (R n4, 0
≤
n4
≤
7)
dst2 indirect ( disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
src2 indirect ( disp = 0, 1, IR0, IR1) or any CPU register
dst1 register (R n1, 0
≤
n1
≤
7)
src3 register (R n2, 0
≤
n2
≤
7)
dst2 indirect ( disp = 0, 1, IR0, IR1)
Opcode
31 24 23 16 8 7 0 15
1 1 0 1 1 1 dst1 src2 dst2 0 count src3
Description The seven LSBs of the count operand are used to generate the 2s-comple-
ment shift count.
If the count operand is greater than 0, a copy of the src2 operand is left shifted
by the value of the count operand, and the result is written to the dst1. (The
src2 is not changed.) Low-order bits shifted in are zero filled, and high-order
bits are shifted out through the carry (C) bit.
Logical left shift:
C
←
src2
←
0
If the count operand is less than 0, the src2 operand is right shifted by the abso-
lute value of the count operand. The high-order bits of the dst operand are 0-
filled as they are shifted to the right. Low-order bits are shifted out through the
C bit.