Lsh3 – Texas Instruments TMS320C3x User Manual
Page 597
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Logical Shift, 3-Operand
LSH3
13-139
Assembly Language Instructions
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 – R0.
LUF
Unaffected
LV
Unaffected
UF
0
N
MSB of the output
Z
1 if a 0 output is generated; 0 otherwise
V
0
C
Set to the value of the last bit shifted out; 0 for a shift
count of 0;
unaffected if
dst is not R7–R0
OVM
Operation is not affected by OVM bit value.
Example 1
LSH3 R4,R7,R2
Before Instruction
After Instruction
R2
00 0000 0000
R2
00 AC00 0000
R4
00 0000 0018
R4
00 0000 0018
R7
00 0000 02AC
R7
00 0000 02AC
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
1
Z
0
Z
0
V
0
V
1
C
0
C
0
24
24
Mode Bit
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