Texas Instruments TMS320C3x - Manual (Page 468)

Instruction Set Summary
13-10
13.2 Instruction Set Summary
Table 13–8 lists the ’C3x instruction set in alphabetical order. Each table entry
provides the instruction mnemonic, description, and operation.
Table 13–8. Instruction Set Summary
Mnemonic Description Operation
ABSF Absolute value of a floating-point number | src|
→
R n
ABSI Absolute value of an integer | src|
→
Dreg
ADDC Add integers with carry src + Dreg + C
→
Dreg
ADDC3 Add integers with carry (3-operand) src1 + src2 + C
→
Dreg
ADDF Add floating-point values src + Rn
→
R n
ADDF3 Add floating-point values (3-operand) src1 + src2
→
R n
ADDI Add integers src + Dreg
→
Dreg
ADDI3 Add integers (3 operand) src1 + src2 +
→
Dreg
AND Bitwise-logical AND Dreg AND src
→
Dreg
AND3 Bitwise-logical AND (3-operand) src1 AND src2
→
Dreg
ANDN Bitwise-logical AND with complement Dreg AND src
→
Dreg
ANDN3 Bitwise-logical ANDN (3-operand) src1 AND src2
→
Dreg
ASH Arithmetic shift If count
≥
0:
(Shifted Dreg left by count)
→
Dreg
Else:
(Shifted Dreg right by | count|)
→
Dreg
ASH3 Arithmetic shift (3-operand) If count
≥
0:
(Shifted src left by count)
→
Dreg
Else:
(Shifted src right by |count|)
→
Dreg
Legend: AR n auxiliary register n (AR7–AR0) RE repeat interrupt register
C carry bit RM repeat mode bit
C src conditional-branch addressing modes R n register address (R7–R0)
count shift value (general addressing modes) RS repeat start register
cond condition code SP stack pointer
Daddr destination memory address Sreg register address (any register)
Dreg register address (any register) ST status register
GIE global interrupt enable register src general addressing modes
N any trap vector 0–27 src1 3-operand addressing modes
PC program counter src2 3-operand addressing modes
RC repeat counter register TOS top of stack