Subf3||stf – Texas Instruments TMS320C3x User Manual
Page 690
SUBF3||STF
Parallel SUBF3 and STF
13-232
Syntax
SUBF3
src1, src2, dst1
||
STF
src3,
dst2
Operation
src2 – src1
→
dst1
||
src3
→
dst2
Operands
src1
register (R
n1, 0
≤
n1
≤
7)
src2
indirect (
disp = 0, 1, IR0, IR1)
dst1
register (R
n2, 0
≤
n2
≤
7)
src3
register (R
n3, 0
≤
n3
≤
7)
dst2
indirect (
disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
-
’C31 silicon revision 6.0 or greater
-
’C32 silicon revision 2.0 or greater
src1
register (R
n1, 0
≤
n1
≤
7)
src2
indirect (
disp = 0, 1, IR0, IR1) or any CPU register
dst1
register (R
n2, 0
≤
n2
≤
7)
src3
register (R
n3, 0
≤
n3
≤
7)
dst2
indirect (
disp = 0, 1, IR0, IR1)
Opcode
31
24 23
16
8 7
0
15
1 1
1 0 1
dst1
1
0
src3
src1
dst2
src2
Description
A floating-point subtraction and a floating-point store are performed in parallel.
All registers are read at the beginning and loaded at the end of the execute
cycle. If one of the parallel operations (STF) reads from a register and the oper-
ation being performed in parallel (SUBF3) writes to the same register, STF ac-
cepts the contents of the register as input before it is modified by the SUBF3.
If
src3 and dst1 point to the same location, src3 is read before the write to dst1.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 – R0.
LUF
1 if a floating-point underflow occurs; unchanged otherwise
LV
1 if a floating-point overflow occurs; unchanged otherwise
UF
1 if a floating-point underflow occurs; 0 otherwise
N
1 if a negative result is generated; 0 otherwise
Z
1 if a 0 result is generated; 0 otherwise
V
1 if a floating-point overflow occurs; 0 otherwise
C
Unaffected
OVM
Operation is not affected by OVM bit value.
Mode Bit