Texas Instruments TMS320C3x - Manual (Page 435)

DMA Controller
12-56
Table 12–6. DMA Global-Control Register Bits Summary (Continued)
Abbreviation
Reset
Value Name Description
DMA0 PRI 00 CPU/DMA channel 0
priority mode (on the DMA0 control register) (’C32 only)
DMA1 PRI
00 CPU/DMA channel 1
priority mode (on the DMA1 control register) (‘C32 only)
Configures CPU/DMA controller priority. (See Section 12.3.6
on page 12-63).
The following table explains the DMA PRI bits and CPU/
DMA priorities.
Bit 13 Bit 12 Function
0 0 DMA has lower priority than the CPU
access. If
the DMA channel and the CPU
are requesting the same resource, the
CPU has priority (reset value).
0 1 Reserved.
1 0 Rotating arbitration, which sets priorities
be
tween the CPU and DMA channel by
alternating their accesses (but not exactly
equally). Priority rotates between the CPU
and DMA accesses when they conflict
during consecutive instruction cycles.
1 1 DMA has higher priority than the CPU
access. Ift
he DMA channel and the CPU
are requesting the same resource, the
DMA has priority.
PRIORITY
MODE 0 DMA channels priority
mode If PRIORITY MODE = 0, fixed priority for the two DMA chan-
nels. DMA channel 0 always has priority over DMA channel 1.
If priority mode = 1, rotating priority for the two DMA channels.
DMA channel 0 has priority after the device is reset. After
reset, the last channel serviced has the lowest priority. The ar-
bitration is performed at DMA service boundaries, that is,
after either a DMA read or DMA write.
See Section 12.3.5 on page 12-62 for more information.