Texas Instruments TMS320C3x - Manual (Page 251)

XF1 = 1,
read must wait
XF1 = 0,
read operation
is complete
Pipeline Conflicts
8-15 Pipeline Operation
Example 8–10. Interlocked Load
NOT R1,R0
LDII 300h,AR
2
ADDI
*AR2,R2
CMPI R0,R2
Pipeline Operation
PC XF1 Fetch Decode Read Execute
n 1 NOT — — —
n+1 1 LDII NOT — —
n+2 1 ADDI LDII NOT —
n+3 1 CMPI ADDI LDII NOT
n+3 1 — CMPI ADDI LDII
n+4 0 — CMPI ADDI LDII
8.2.3.4 Hold Everything
Three situations result in hold-everything memory pipeline conflicts:
- A CPU data load or store cannot be performed because an external port
is busy.
- An external load takes more than one cycle.
- Conditional calls and traps, which take one more cycle than conditional
branches, are processed.
The first type of hold-everything conflict occurs when one of the external ports
is busy because an access has started, but is not complete. In Example 8–11,
the first store is a 2-cycle store. The CPU writes the data to an external port.
The port control then takes two cycles to complete the data-data write. The
LDF is a read over the same external port. Since the store is not complete, the
CPU continues to attempt LDF until the port is available.