Texas Instruments TMS320C3x - Manual (Page 87)

Memory
4-5 Memory and the Instruction Cache
4.1.1.2 TMS320C31 Memory Map
The memory map depends on whether the processor is running in micropro-
cessor mode (MCBL/MP = 0) or microcomputer mode (MCBL/MP = 1). The
memory maps for these modes are similar (see Figure 4–2 on page 4-6).
Locations 800000h–807FFFh are reserved. All of the memory-mapped
peripheral bus registers are in locations 808000h–8097FFh. In both modes,
RAM block 0 is located at addresses 809800h–809BFFh, and RAM block 1 is
located at addresses 809C00h–809FFFh. Locations 80A000h–0FFFFFFh
are accessed over the external memory port (STRB active).
- Microprocessor Mode
In microprocessor mode, the boot loader is not mapped into the ’C3x
memory map. Locations 0h–03Fh consist of interrupt vector, trap vector,
and reserved locations, all of which are accessed over the external
memory port (STRB active) (see Figure 4–2 on page 4-6). Locations
040h–7FFFFFh are also accessed over the external memory port.
- Microcomputer Mode
In microcomputer mode, the boot loader ROM is mapped into locations
0h–0FFFh. The last 63 words (809FC1h to 809FFFh) of internal RAM
Block 1 are used for interrupt and trap
branches (see Figure 4–2 on page
4-6). Locations 1000h–7FFFFFh are accessed over the external
memory port (STRB active).
Section 4.1.2, Peripheral Bus Memory Map, on page 4-9 describes the
peripheral memory maps in greater detail and Section 4.2, Reset/Interrupt/
Trap Vector Map, on page 4-14 provides the vector locations for reset, inter-
rupts, and traps.
Be careful! Access to a reserved area produces unpredictable
results.