Texas Instruments TMS320C3x - Manual (Page 573)

Load Floating-Point Value Conditionally LDFcond
13-115 Assembly Language Instructions
Syntax LDF cond src, dst
Operation If cond is true:
src
→
dst.
Else:
dst is unchanged.
Operands src general addressing modes (G):
0 0 register (R n, 0
≤
n
≤
7)
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst register (R n, 0
≤
n
≤
7)
Opcode
31 24 23 16 8 7 0 15
0 1 0 0 cond dst src G
Description If the condition is true, the src operand is loaded into the dst register; otherwise,
the dst register is unchanged. The dst and src operands are assumed to be
floating-point numbers.
The ’C3x provides 20 condition codes that can be used with this instruction
(see Table 13–12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Note that an LDFU (load floating-point unconditionally) in-
struction is useful for loading R7–R0 without affecting condition flags. Condi-
tion flags are set on a previous instruction only when the destination register
is one of the extended-precision registers (R7–R0) or when one of the com-
pare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB, or TSTB3) is ex-
ecuted.
Cycles 1
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value. Mode Bit