Texas Instruments TMS320C3x - Manual (Page 261)

Clocking Memory Accesses
8-25 Pipeline Operation
See Chapter 6, Addressing Modes, for more information.
As discussed in Chapter 7, the number of bus cycles for external memory
accesses differs in some cases from the number of CPU execution cycles. For
external reads, the number of bus cycles and CPU execution cycles is identical.
For external writes, there are always at least two bus cycles, but unless there
is a port-access conflict, there is only one CPU execution cycle. In the following
examples, any difference in the number of bus cycles and CPU cycles is noted.
8.5.2.1 2-Operand Instruction Memory Accesses
All instructions whose bits 31–29 are 000 or 010 (see Figure 8–3) are 2-operand
instructions. In the case of a data read, bits 15–0 represent the
src operand.
Internal data reads are always performed during H1. External data reads always
start at the beginning of H3 with the address presented on the external bus; they
complete with the latching of the data word at the end of H1.
In the case of a data store, bits 15–0 represent the dst operand. Internal data
stores are performed during H3. External data stores always start at the
beginning of H3 with the address and data being presented on the external bus.
Figure 8–3. 2-Operand Instruction Word
31
0 X 0 Operation dst(src) G src(dst)
24 23 16 15 8 7 0
8.5.2.2 3-Operand Instruction Memory Reads
All instructions whose bits 31–29 are 001 (see Figure 8–4) are 3-operand
instructions. The source operands,
src1 and src2, come from either registers
or memory. When one or more of the source operands are from memory, these
instructions are always memory reads.
Figure 8–4. 3-Operand Instruction Word
31
0 0 1 Operation dst T
24 23 16 15 8 7 0
src1 src2
If only one of the source operands is from memory (either src1 or src2) and is
located in internal memory, the data is read during H1. If the single memory
source operand is in external memory, the read starts at the beginning of H3,
with the address presented on the external bus, and completes with the latching
of the data word at the end of H1.