Texas Instruments TMS320C3x - Manual (Page 445)

DMA Controller
12-66
Figure 12–44. Mechanism for DMA Source Synchronization
Start
Disable DMA interrupts globally
DMA channel performs a read
DMA channel performs a write
Go to start
Enable DMA interrupts globally
Idle until enabled interrupt is received
Clear corresponding IF bit
- Destination synchronization (SYNC = 1 0)
When SYNC = 1 0, the DMA is synchronized to the destination. First, all
interrupts are ignored until the read is complete. Though the DMA interrupts
are considered globally disabled, no bits in the DMA interrupt-enable regis-
ter are changed. A write is not performed until an interrupt is received by the
DMA, while the read is performed without waiting for the interrupt.
Figure 12–45 shows the synchronization mechanism when SYNC = 1 0.
Figure 12–45. Mechanism for DMA Destination Synchronization
Start
Disable DMA interrupts globally
DMA channel performs a read
DMA channel performs a write
Go to start
Idle until enabled interrupt is received
DMA interrupts are enabled globally
Clear corresponding IF bit