Texas Instruments TMS320C3x - Manual (Page 591)

Load Floating-Point Mantissa LDM
13-133 Assembly Language Instructions
Syntax LDM src, dst
Operation src (man)
→
dst (man)
Operands src general addressing modes (G):
0 0 register (R n, 0
≤
n
≤
7)
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst register (R n, 0
≤
n
≤
7)
Opcode
31 24 23 16 8 7 0 15
0 0 0 0 1 1 0 0 0 dst src G
Description The mantissa field of the src operand is loaded into the mantissa field of the
dst register. The dst exponent field is not modified. The src and dst operands
are assumed to be floating-point numbers. If the
src operand is from memory,
the entire memory contents are loaded as the mantissa. If immediate address-
ing mode is used, bits 15–12 of the instruction word are forced to 0 by the as-
sembler.
Cycles 1
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.
Example LDM 156.75,R2 (156.75 = 071CC00000h)
Before Instruction After Instruction
R2 00 0000 0000 R2 00 1CC0 0000
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
1.22460938e+00
Mode Bit