Texas Instruments TMS320C3x - Manual (Page 239)

Pipeline Structure
8-3 Pipeline Operation
For ‘C30 and ‘C31, priorities from highest to lowest have been assigned to
each of the functional units of the pipeline and to the DMA controller as follows:
- Execute (highest)
- Read
- Decode
- Fetch
- DMA (lowest)
Despite the DMA controller’s low priority, you can minimize or even eliminate
conflicts with the CPU through suitable data structuring because the DMA con-
troller has its own data and address buses.
In the ‘C32, the DMA has configurable priorities. Therefore, priorities from
highest to lowest have been assigned to each of the functioned units of the
pipeline and to the DMA controller as follows:
- DMA (if configured with highest priority)
- Execute
- Read
- Decode
- Fetch
- DMA (if configured with lowest priority)
A pipeline conflict occurs when an instruction is being processed, and is ready
to pass to the next higher pipeline level while that level is not ready to accept
a new input. In this case, the lower priority unit waits until the higher priority unit
completes executing the current function.